I. Technical Field
The present invention relates to electronic memories and more particularly to modular memories having a plurality of semiconductor integrated circuits for the storage and retrieval of words of binary data.
II. Description of the Related Art
High-speed random access memory for digital computers is typically provided by dynamic random access semiconductor memory chips, known in the art as "DRAMs." To achieve a high packing density of DRAMs in a computer system, a main memory unit for a digital computer typically includes a plurality of memory modules, each of which is comprised of a plurality of DRAMs mounted on a printed wiring board. The printed wiring boards are mounted at an angle with respect to a so-called "mother" board. The DRAMs of a memory module are typically mounted on both sides of the printed wiring board, and the printed wiring board has an edge portion with a series of terminals for connection to the motherboard. The DRAMs have address inputs which are wired in parallel to address lines. The individual DRAMs on the printed wiring board are selected by row address strobe (RAS) and column address strobe (CAS) signals. The DRAMs on the printed wiring board are subdivided into groups called "strings" such that all of the DRAMs in a string share the same RAS and CAS signals and therefore simultaneously read or write data at the same address to or from a data bus. In particular, a DRAM will read or write data in response to the column address strobe.
Due to continual improvements in semiconductor fabrication technology, it is possible to store an increasing amount of data on a single DRAM chip and, at the same time, the power dissipation per bit of storage has decreased and the speed of data access has increased. Consequently, it is possible to pack a large number of DRAM chips into a very small volume without running into power dissipation problems, yet there is a difficulty in providing address, data, and control connections to the chips in such a dense packing configuration. Therefore, memory designers are presented with the problem of obtaining high packing densities without introducing manufacturing difficulties or causing noise due to cross-coupling or reflections on the interconnecting lines carrying the high-speed address, data and control signals.